Forget the hand-crafting! In today’s fast-moving consumer electronics industry, achieving short time-to-market is the single most effective way of maximizing semiconductor sales and profit. The chances are you will still be able to push the SoC down the price curve by migrating it to a next-generation CMOS process technology within 18 months or so.

In addition to providing cost-down on existing designs, each new CMOS process is going to allow the design of ever more complex chips. Reducing time-to-market for these new designs will therefore require you to manage an ever-increasing level of complexity in a way that cuts both design and verification times.

There will need to be aggressive changes in the way SoC designs are driven within the industry, together with partnerships between companies to drive forward standards for IP inter-operability. The Spirit (Structure for Packaging, Integrating and Re-using IP within Tool-flows) consortium, a group of leading companies in the IP supply chain that includes EDA tool vendors, IP providers and integrated device manufacturers, is one example of current collaboration in this area.

However, any such standards will only gain widespread acceptance if they are effectively deployed within companies and their ability to accelerate the chip design process is proven. One of the essential enablers for this is a mechanism that makes properly configured re-usable IP available to chip designers in a way that allows them to easily select it, understand it and import it into their SoC design environment. The more comprehensive the selection, the more powerful and effective the IP library is.

IP Yellow Pages

One such system being developed by Philips for its internal design teams is a service called "IP Yellow Pages." This web-based service, which is hosted on a secure sever, allows Philips’ chip designers to browse the company’s IP libraries and to locate suitable IP with the aid of a search engine.

For each library entry, an IP Profile web page provides an overview of the IP’s attributes, documentation, deliverables, development status and level of support. If applicable, it also details any associated usage, maintenance and royalty fees. Chip designers can then download the IP they require from the server via a web-based or command-line interface.

The IP Yellow Pages web-site includes both hardware and software IP and will soon allow the ordering and order-tracking of use-specific memory configurations. The site also acts as a shop window for the promotion of new IP that is added to the IP Yellow Pages library. Much of the IP available through the IP Yellow Pages service is already Spirit compliant.

It is equally important to have a system that allows you to assemble the selected IP speedily into a SoC design. To manage the competing requirements of increasing complexity and shorter time-to-market, this design environment must be capable of taking SoC design to the next level of abstraction by allowing the rapid generation, configuration and verification of re-usable sub-systems.

It must be able to address system architecture considerations as well as IP block assembly, steering designers towards sub-system and SoC architectures that are suited both to the application and to the available IP. To cope with the increasing use of IP from third-party IP vendors and joint-ventures, it should be based on industry standards for IP re-use and commercially supported EDA tools.

These underlying principles are illustrated by Philips Semiconductors’ new Nx-Builder design (Figure 1). Nx-Builder is built around a set of Spirit compliant EDA tools – Mentor Graphics’ Platform Express XML-based SoC design creation tool framework, Synopsys’ synthesis and automated scripting tools and Prosilog’s GUI-based Magillem SoC design tools for the SPIRIT packaging of IP.

Figure 1— Philips Semiconductors' Nx-Builder SoC design environment

Nx-Builder uses Philips Semiconductors’ SPIRIT-compliant IP Yellow Pages as its IP portfolio. These components combine to create an environment in which SoC design becomes almost a drag-and-drop exercise. By doing so it is pushing the boundaries of automated integration and validation to new levels.

The benefits of such a system are considerable. Design and verification cycles are significantly reduced, with functions such as interconnect verification, infrastructure verification (busses, bridges, memories, register spaces) and IP interoperability being almost fully automated. Chip composition and parameter derivation for reconfigurable IP is improved, and the system provides a single source for system documentation (flow-scripts, memory maps, interrupt maps, register specifications).

Such systems not only reduce design risk and encourage future IP re-use. They also enable highly efficient platform reuse. By providing automated generation of high-quality documentation coupled with a high-level of design automation, they generate chip designs that are far less dependent on a single design engineer. Time-to-market reduction can be as much as 25% for new SoC designs, and 75% for straightforward derivatives.

Pathway to ESL

Simplifying and automating SoC design by an order of magnitude compared to previous methods, environments such as Nx-Builder pave the way for ESL (Electronic System Level) design — the next paradigm shift in the industry. Targeted at high-level hardware/software co-design, ESL design libraries feature SystemC descriptions of library components (Figure 2). Because these provide behavioral models for hardware IP in a language that is essentially the same as the software languages used to program SoCs (C or C++), these ESL design environments will allow you to simulate and verify your entire hardware/software design before having to lock anything into silicon.

As a result, they will allow you to make critical hardware/software trade-offs very early on in the design cycle, thereby minimizing design risk. They will also give you the benefits of advanced features such as automatic selection of appropriate system architectures, intelligent debugging and automated optimization of RTL output from high-level functional descriptions/models.

In conjunction with compiler development environments that can automatically generate compilers from SystemC descriptions, ESL design environments will even allow you to customize software instruction sets to suit specific architectures and application requirements. These new possibilities will provide an optimum approach that combines mature IP reuse with innovative design and new IP creation.

In a business environment where semiconductor companies already have to provide comprehensive software stacks with their SoCs simply to sell silicon, the ability to minimize risk and shorten time-to-market through hardware/software co-design will be an important new enabler for differentiation.

Ralph von Vignau is Director of Infrastructure and Standards, Chief Technology Office, Philips Semiconductors.